INTEL VT-D Root table and context table relationship
I am trying to learn about INTEL VT-D, I've read that root table has 256 entries, with each root table points to furhter context table with 256 entries each, where each context table contains second level translation. Unfortunately I am unable to figure out the exact relationship between root table and context table. Do we have 256 * 256 context table entries ? or each root table points to same context table. By looking into following figure, 
It says each context table has different bus number, but i am unable to relate to it, also it would be great if someone tells about second level translation, I am fimilar with MMU paging but VT-D paging is really confusing. I have gone through VT-D specs but still some concepts are not clear which I described above.
x86 intel virtualization dma iommu
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
add a comment |
I am trying to learn about INTEL VT-D, I've read that root table has 256 entries, with each root table points to furhter context table with 256 entries each, where each context table contains second level translation. Unfortunately I am unable to figure out the exact relationship between root table and context table. Do we have 256 * 256 context table entries ? or each root table points to same context table. By looking into following figure,
It says each context table has different bus number, but i am unable to relate to it, also it would be great if someone tells about second level translation, I am fimilar with MMU paging but VT-D paging is really confusing. I have gone through VT-D specs but still some concepts are not clear which I described above.
x86 intel virtualization dma iommu
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
add a comment |
I am trying to learn about INTEL VT-D, I've read that root table has 256 entries, with each root table points to furhter context table with 256 entries each, where each context table contains second level translation. Unfortunately I am unable to figure out the exact relationship between root table and context table. Do we have 256 * 256 context table entries ? or each root table points to same context table. By looking into following figure,
It says each context table has different bus number, but i am unable to relate to it, also it would be great if someone tells about second level translation, I am fimilar with MMU paging but VT-D paging is really confusing. I have gone through VT-D specs but still some concepts are not clear which I described above.
x86 intel virtualization dma iommu
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
I am trying to learn about INTEL VT-D, I've read that root table has 256 entries, with each root table points to furhter context table with 256 entries each, where each context table contains second level translation. Unfortunately I am unable to figure out the exact relationship between root table and context table. Do we have 256 * 256 context table entries ? or each root table points to same context table. By looking into following figure,
It says each context table has different bus number, but i am unable to relate to it, also it would be great if someone tells about second level translation, I am fimilar with MMU paging but VT-D paging is really confusing. I have gone through VT-D specs but still some concepts are not clear which I described above.
x86 intel virtualization dma iommu
x86 intel virtualization dma iommu
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
edited Nov 14 '18 at 12:11
Peter Cordes
119k16181308
119k16181308
asked Nov 14 '18 at 6:52
Ameer Hamza
236
asked Nov 14 '18 at 6:52
Ameer Hamza
236
asked Nov 14 '18 at 6:52
Ameer Hamza
236
236
add a comment |
add a comment |
1 Answer
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In PCIe, there are 256 bus numbers, and 256 device/function numbers per bus, for a total of 256*256 functions. In VT-d, there can be a context entry for each of these.
The root table/context tables are organized as a two-level table so that the context tables don't have to be fully populated. Each root table entry has a present bit. If the present bit is 0, there is no context table for that bus.
It would be highly unusual for more than one root table entry to point to the same context table, although there is nothing to preclude it.
If you are familiar with CPU paging, the VT-d page table structures are very similar to EPT (and in fact the same physical tables in memory can be used for both purposes simultaneously). VT-d supports two-, three-, or four-level paging structures with up to 48-bit addresses (depending on the hardware implementation; I believe that all current implementations support 4-level walks only).
If you have more specific questions, I can answer them, but I don't think this is a good place for a tutorial.
answered Nov 20 '18 at 1:15
prl
4,4631315
add a comment |
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1 Answer
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1 Answer
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In PCIe, there are 256 bus numbers, and 256 device/function numbers per bus, for a total of 256*256 functions. In VT-d, there can be a context entry for each of these.
The root table/context tables are organized as a two-level table so that the context tables don't have to be fully populated. Each root table entry has a present bit. If the present bit is 0, there is no context table for that bus.
It would be highly unusual for more than one root table entry to point to the same context table, although there is nothing to preclude it.
If you are familiar with CPU paging, the VT-d page table structures are very similar to EPT (and in fact the same physical tables in memory can be used for both purposes simultaneously). VT-d supports two-, three-, or four-level paging structures with up to 48-bit addresses (depending on the hardware implementation; I believe that all current implementations support 4-level walks only).
If you have more specific questions, I can answer them, but I don't think this is a good place for a tutorial.
answered Nov 20 '18 at 1:15
prl
4,4631315
add a comment |
In PCIe, there are 256 bus numbers, and 256 device/function numbers per bus, for a total of 256*256 functions. In VT-d, there can be a context entry for each of these.
The root table/context tables are organized as a two-level table so that the context tables don't have to be fully populated. Each root table entry has a present bit. If the present bit is 0, there is no context table for that bus.
It would be highly unusual for more than one root table entry to point to the same context table, although there is nothing to preclude it.
If you are familiar with CPU paging, the VT-d page table structures are very similar to EPT (and in fact the same physical tables in memory can be used for both purposes simultaneously). VT-d supports two-, three-, or four-level paging structures with up to 48-bit addresses (depending on the hardware implementation; I believe that all current implementations support 4-level walks only).
If you have more specific questions, I can answer them, but I don't think this is a good place for a tutorial.
answered Nov 20 '18 at 1:15
prl
4,4631315
add a comment |
In PCIe, there are 256 bus numbers, and 256 device/function numbers per bus, for a total of 256*256 functions. In VT-d, there can be a context entry for each of these.
The root table/context tables are organized as a two-level table so that the context tables don't have to be fully populated. Each root table entry has a present bit. If the present bit is 0, there is no context table for that bus.
It would be highly unusual for more than one root table entry to point to the same context table, although there is nothing to preclude it.
If you are familiar with CPU paging, the VT-d page table structures are very similar to EPT (and in fact the same physical tables in memory can be used for both purposes simultaneously). VT-d supports two-, three-, or four-level paging structures with up to 48-bit addresses (depending on the hardware implementation; I believe that all current implementations support 4-level walks only).
If you have more specific questions, I can answer them, but I don't think this is a good place for a tutorial.
answered Nov 20 '18 at 1:15
prl
4,4631315
In PCIe, there are 256 bus numbers, and 256 device/function numbers per bus, for a total of 256*256 functions. In VT-d, there can be a context entry for each of these.
The root table/context tables are organized as a two-level table so that the context tables don't have to be fully populated. Each root table entry has a present bit. If the present bit is 0, there is no context table for that bus.
It would be highly unusual for more than one root table entry to point to the same context table, although there is nothing to preclude it.
If you are familiar with CPU paging, the VT-d page table structures are very similar to EPT (and in fact the same physical tables in memory can be used for both purposes simultaneously). VT-d supports two-, three-, or four-level paging structures with up to 48-bit addresses (depending on the hardware implementation; I believe that all current implementations support 4-level walks only).
If you have more specific questions, I can answer them, but I don't think this is a good place for a tutorial.
answered Nov 20 '18 at 1:15
prl
4,4631315
answered Nov 20 '18 at 1:15
prl
4,4631315
answered Nov 20 '18 at 1:15
prl
4,4631315
answered Nov 20 '18 at 1:15
prl
4,4631315
4,4631315
add a comment |
add a comment |
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